This invention relates to a logic simulator for use in simulating operation of a logic device, which may be an electronic digital computer comprising a central processing unit, a main memory, a cache memory, and microprogram memories.
As will later be described with reference to one of several figures of the accompanying drawing, the logic device is used for carrying out an overall logic operation on a device input signal to provide a device output signal. Such a logic device is divisible into a plurality of logic blocks which have block input and output terminals and are themselves used for carrying out a first predetermined number of individual logic operations on input logic states of the block input terminals to provide output logic states of the block output terminals. The (block) input and output terminals are connected to one another in a predetermined manner of connection to receive the device input signal and to produce the device output signal. By way of example, a logic device may be divisible into more than ten thousand IC memories.
The device input signal may comprise a plurality of individual device input signals and the device output signal, a plurality of individual device output signals. Each logic block has at least one input terminal and at least one output terminal. It is to be noted as regards the predetermined manner of connection that an output terminal of a logic block is not ordinarily connected to any input terminal thereof but either to one or more input terminals of another logic block or to input terminals of other logic blocks and that each individual device input (output) signal is for at least one input (output) terminal of at least one logic block. Each individual logic operation need not be a single AND operation for two or more input logic states, a single inverting operation, or the like single operation but may be a combination of such single logic operations.
On simulating the overall logic operation by a logic simulator according to this invention, the logic blocks are identified by block numbers, respectively. The block input and output terminals are identified by block input and output terminal numbers, respectively. One and the same block input terminal number may be used in common for input terminals of different logic blocks. Even in this event, it is possible to understand that such input terminals are identified by different block input terminal numbers, respectively, because the logic blocks are identified by different block numbers, respectively.
The individual logic operations are identified by respective types. It is convenient to assign the types to the respective logic blocks rather than to the respective individual logic operations. Similarly, it is desirable to allot the input logic states to the respective block input terminals and consequently to the respective block input terminal numbers and the output logic state to the respective block output terminal numbers.
The predetermined manner of connection between a block output (input) terminal and at least one block input (output) terminal is defined by a combination of a block output (input) terminal number and at least one block input (output) terminal number. It is therefore possible to define the predetermined manner of connection by such combinations.
The input logic state of an input terminal of a logic block is dependent on at least one previously carried out individual logic operation. In other words, the input logic state is decided by the number of logic blocks through which an individual device input signal reaches the block input terminal. The logic blocks are given a second predetermined number of level numbers in consideration of the predetermined manner of connection. For example, the level number of a logic block is given by a maximum number of the logic blocks through which an individual device input signal arrives at a certain input terminal of the logic block under consideration.
On designing a logic device, an error or defect, if any, in the logic or circuitry design should be discovered or detected as early as possible during progress of the design. Otherwise, the design is subject to a serious delay and also to an intolerable expense. This is because correction or change of circuitry is very troublesome and difficult after a logic device is actually manufactured. This is also the case with debugging of a program. Such a diagnosis operation for the design error or errors must rapidly be carried out even for a complicated overall logic operation of a logic device.
A logic simulator is very effective in error diagnosis of an overall or a partial logic operation of a logic device. With a logic simulator, it is possible to find the design error without actually manufacturing the logic device in compliance with a possibly erroneous design.
A conventional logic simulator is mostly based on software. The individual logic operations have actually been conventionally carried out in sequence. The sequential process has resulted in a long simulation time when the simulation must be carried through for an overall logic operation of a large logic scale.